1. Field of the Invention
The present invention relates to improved means to interconnect semiconductor devices or chips carried on an appropriate substrate to a complementary printed circuit card.
2. Development of the Invention
It is well known in the semiconductor art to mount a semiconductor device on a ceramic substrate and to interconnect the same to a printed circuit card employing pins attached to the underside of the substrate which are in electrical contact with the semiconductor device by via holes in the substrate. The pins on the underside of the substrate mate with plated-through-holes located in the printed circuit card. Using current state of the art technology, practical densities for pin structures with area array pin groups is commonly accepted to be 0.1 inch. Attempts to decrease pin spacings below 0.1 inch generally result in stringent manufacturing tolerances, high cost, and increased laminating levels to compensate for D.C. drops and wiring losses caused by the increased plated-through-hole density.
Increasing the number of pins on the underside of the substrate requires a corresponding increase in plated-through-holes in the related printed circuit card. The pins are usually reflow soldered within the plated-through-holes in the card. Increasing the number of pins improves the thermal conduction path from the plated-through-holes through the internal power planes in the printed circuit card. This can result in the need for higher than desirable heating in order to remove a pinned substrate from a printed circuit card. Some secondary effects of this higher required substrate removal temperature are: higher pin and plated-through-hole stress due to differences in thermal expansion coefficients of the materials involved, printed wiring may become electrically discontinuous and plated-through-holes may crack along the "Z" axis.
Increasing the number of pins on the underside of a ceramic substrate is usually achieved by maintaining the basic pin spacing at a 0.100 inch spacing which requires a larger ceramic substrate, a costlier item, and more printed circuit card real estate for mounting. Attempts to reduce the pin spacing from 0.100 inch will usually result in wiring channel blockage within the printed circuit card. While wiring channel blockage may be compensated for by increasing the number of wiring planes internal to the printed circuit card, this is also a costly solution. Further, considering the general trend in the art to higher performance circuitry, increasing the number of internal wiring planes in a printed circuit card would most likely require a change from micro-strip transmission lines to a tri-plate transmission line configuration which would result in a further requirement for more internal metal layers to act as A.C. reference planes. Finally, the use of a tri-plate structure would increase the relative amount of dielectric material (epoxy-glass) required and result in a negative aspect ratio of plated-through-hole diameter to printed circuit card thickness, again resulting in an increase in cost.
U.S. Pat. No. 3,594,619 Kamoshida et al relates to a beam lead chip for face bonding to chip carriers. Its primary feature is thermal enhancement, i.e., effecting improved thermal capability by creating electrically passive contacts within a beam lead free region of the chip and providing for face bonding of the contacts to a ceramic carrier substrate. Alternatively, additional beam leads may be employed as thermal paths between the chip and the ceramic carrier substrate. Such a device is self-limiting in that as the electrical interconnection requirement increases the redundant thermal contacts must decrease. The Kamoshida et al invention may be likened to the practice of using dummy controlled collapse solder joints on face bonded chips, except Kamoshida et al do not have the placement freedom nor the efficiency of application of such a procedure.
The present invention may employ a thermal grease over the entire chip surface so that the primary thermal path is from the back of the chip to a protective cover. Hence, thermal flux through the membrane of the carrier is secondary and minimal.
U.S. Pat. No. 3,614,832 Chance et al describes a means for bonding and transferring peripherally disposed electrical jumpers from a semiconductor die to a ceramic carrier. The insulating element of the disclosed decal transfer device is removed by use of a solvent. The removal of the insulating material precludes the option of multi-layer wiring capability as disclosed herein.
U.S. Pat. No. 3,624,462 Phy relates to a semiconductor photo-array structure which relies on a face bonding technique between the semiconductor and its carrier. The carrier contains a fused bundle of short fiber optic elements for effecting the transmission of distinct packets of light with minimal or no optical cross talk. This is a rigid face-bonded mounting solution that does not relate to the compliant membrane of the present invention.
U.S. Pat. No. 3,662,230 Redwants relates to a hermetic package having a header with pins formed so as to effect surface contact to a supporting printed circuit card. A semiconductor chip is "back down" bonded to the header and a thin film wiring system is used on the top side of the semiconductor to provide electrical paths from the semiconductor chip to the ends of the appropriate header pins. Redwantz still employs pins to connect the hermetic carrier to a circuit card whereas one objective of the present invention is to eliminate the need for pins between a carrier and a supporting printed circuit card.
U.S. Pat. No. 3,780,352 Redwants is a division of U.S. Pat. No. 3,662,230 above discussed. Hence, comments applicable to U.S. Pat. No. 3,662,230 are also pertinent to U.S. Pat. No. 3,780,352.
U.S. Pat. No. 3,868,724 Perrino relates to the structure commonly known in the industry today as tape-automated-bonding. This semiconductor interconnection scheme basically comprises a reel mounted continuous tape having sprocket holes disposed along its edges for incremental advance. This tape is personalized so as to have a printed beam lead on a single surface of the tape to which semiconductor dies are bonded, transported, tested, burned-in and eventually encapsulated, excised and attached to or serve as a carrier for. This structure is not suited to area array interconnection nor multilevel wire escape from the semiconductor and is vastly different from the invention herein.
IBM TDB, Vol. 21, No. 2, July '78, P. 569 describes a film device which has some similarity to the membrane of the present invention, but the device of the TDB is primarily constructed integral to a pair of semiconductor dies with the objective, specifically in a memory system, of sharing the pins on a ceramic carrier while allowing for each semiconductor to be maintained in intimate contact with a metallic protective cover for effecting an optimal thermal dissipation path. The film member of the TDB is not employed on a ceramic carrier with the intent of eliminating the carrier pins and making improvements in a related circuit card as per the present invention.